Circuit
Processing-in-memory
IEEE European Solid-State Electronics Research Conference (ESSERC), 2025
Hoichang Jeong*, Seungbin Kim*, Jueun Jung, and Kyuho Jason Lee (*equal contribution)
Research Area
Automotive System
Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.
DNN Accelerator
Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.
Processing-in-Memory
Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.
Neuromorphic
The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.
Recent Conference Paper
Circuit
Processing-in-memory
IEEE European Solid-State Electronics Research Conference (ESSERC), 2025
Hoichang Jeong*, Seungbin Kim*, Jueun Jung, and Kyuho Jason Lee (*equal contribution)
Circuit
Multi Camera System
BEVSA: A Real-Time Bird’s-Eye-View Semantic Segmentation Accelerator for Multi-Camera System
ACM/IEEE Design Automation Conference (DAC), 2025
Sangho Lee, Jueun Jung, Wuyoung Jang, Jihyeon Hwang, and Kyuho Lee
Recent Journal Paper
Circuit
Processing-in-memory
HYTEC: Compact and Energy-Efficient Analog-Digital Hybrid CIM With Transpose Ternary eDRAM
IEEE Journal of Solid-State Circuits (JSSC), (Early Access), 2025
Hoichang Jeong, Seungbin Kim, Jeongmin Shin, and Kyuho Jason Lee
Circuit
Processing-in-memory
Large-language-Model
IEEE Transactions on Very Large Scale Integration (T-VLSI), (Early Access), 2025
Sunhong An, Hoichang Jeong, Seungbin Kim, and Kyuho Jason Lee
Good times at ISL
Intelligent Systems Lab
2025-10-31
The first Tokyo–Yonsei Workshop with Prof. Atsutake Kosuge at Tokyo University was a great success. Thank you all for sharing your knowledge and building friendship through this wonderful collaboration.