Intelligent Systems Lab

In the realm of modern computing, our aim is to advance systems based on specialized hardware. Research spans various fields of hardware design, including computer architecture, VLSI, FPGA, hardware/software co-design, and processing-in-memory. We adopt a holistic approach to enhance overall system performance. Our current mission centers on building a high-performance and scalable computing platform for future AI applications.

Automotive System

Spatial AI is crucial for autonomous vehicle safety but high computational power consumption reduces driving range. Our research focuses on energy-efficient methods using HW-SW co-design and sensor-friendly AI SoCs to enhance autonomous driving efficiency and safety.

DNN Accelerator

Hand gesture recognition (HGR) using 3D-CNNs and super resolution (SR) with deep neural networks both demand significant computational power, posing challenges for real-time processing on mobile devices. Dedicated ASIC processors are needed to enable efficient HGR and SR on battery-limited devices.

Processing-in-Memory

Convolutional Neural Networks (CNNs) excel in image and video processing but are limited by high computational and memory demands. Computing-in-Memory (CIM) architecture offers a solution by processing data within on-chip memory, significantly enhancing throughput and energy efficiency for ultra-low-power IoT devices.

Neuromorphic

The human brain consumes only 20 mW with 1 billion neurons in computation. Spiking Neural Networks (SNNs) mimic the behavior of biological neural networks to reduce power consumption of Artificial Neural Networks (ANNs). Neuromorphic processors accelerates SNNs for ultra low power hardware such as always-on-sensors, surveilance monitoring, bio-sensor back-end.

Recent Conference Paper

47

Major

ESSERC

Circuit

Processing-in-memory

Hybrid eDRAM CIM by Effective Row Activation with Simultaneous Multi-Row-Multi-Task Control

IEEE European Solid-State Electronics Research Conference(ESSERC), 2025

Hoichang Jeong*, Seungbin Kim*, Jueun Jung, and Kyuho Jason Lee (*equal contribution)

46

Top-Tier

DAC

Circuit

Multi Camera System

BEVSA: A Real-Time Bird’s-Eye-View Semantic Segmentation Accelerator for Multi-Camera System

ACM/IEEE Design Automation Conference(DAC), 2025

Sangho Lee, Jueun Jung, Wuyoung Jang, Jihyeon Hwang, and Kyuho Lee

Recent Journal Paper

23

Top-Tier

JSSC

Circuit

PointCloud Neural Network

Lidar

A LiDAR-PNN Pipelined Processor with Cylindrical Bin Partitioning and Halo Indexing for 3D Perception in Outdoor Autonomous Driving Applications

IEEE Journal of Solid-State Circuits (JSSC), 2025

Bokyoung Seo, Jueun Jung, Donghyeon Han, and Kyuho Jason Lee

22

Top-Tier

T-CAS I

Circuit

Processing-in-memory

PointCloud Neural Network

Lidar

IEEE Transactions on Circuits and Systems I (T-CAS I) (Early Access), 2025

Jeongmin Shin, Hoichang Jeong, Seungbin Kim, Keonhee Park, Sangho Lee, and Kyuho Jason Lee